CD4081B data sheet, product information and support (2024)

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4-ch 2-input 3-V to 18-V AND gate CD4081B Product details Similar products you might be interested in Technical documentation Design & development Ordering & quality Support & training References
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Logic gates

AND gates

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4-ch 2-input 3-V to 18-V AND gate

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Data sheet

  • document-pdfAcrobat CD4073B, CD4081B, CD4082B TYPES datasheet (Rev. C)

CD4081B

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Data sheet Order now

Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 6.8 IOH (max) (mA) -6.8 Input type Standard CMOS Output type Push-Pull Features High speed (tpd 10- 50ns) Data rate (max) (Mbps) 8 Rating Catalog Operating temperature range (°C) -55 to 125

Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 6.8 IOH (max) (mA) -6.8 Input type Standard CMOS Output type Push-Pull Features High speed (tpd 10- 50ns) Data rate (max) (Mbps) 8 Rating Catalog Operating temperature range (°C) -55 to 125

PDIP (N) 14 181.42 mm² 19.3 x 9.4 SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range: 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Standardized, symmetrical output characteristics
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

CD4073B Triple 3-Input AND Gate
CD4081B Quad 2-Input AND Gate
CD4082B Dual 4-Input AND Gate
Data sheet acquired from Harris Semiconductor
  • Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range: 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Standardized, symmetrical output characteristics
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

CD4073B Triple 3-Input AND Gate
CD4081B Quad 2-Input AND Gate
CD4082B Dual 4-Input AND Gate
Data sheet acquired from Harris Semiconductor

CD4073B, CD4081B and CD4082B AND gates, provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates.

The CD4073B, CD4081B, and CD4082B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4073B, CD4081B and CD4082B AND gates, provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates.

The CD4073B, CD4081B, and CD4082B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

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Drop-in replacement with upgraded functionality to the compared device
SN74LVC08A ACTIVE Four-channel two-input 1.65V to 3.6V AND gate Smaller voltage range (1.65V to 5.5V), shorter average propagation delay (5.5ns), higher average drive strength (24mA)

Technical documentation

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Type Title Date
* Data sheet CD4073B, CD4081B, CD4082B TYPES datasheet (Rev. C) 21 Aug 2003
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 03 Dec 2001

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module(EVM)is designed to support any logic device that is in a 14-pin to 24-pinD, DW, DB, NS, PW, DYYor DGV package,

User guide: PDF | HTML

Not available on TI.com

Simulation model

CD4081B Behavioral SPICE Model (Rev. A)

SCHM010A.ZIP (7 KB) - PSpice Model

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Simulation model

CD4081B PSPICE Model

SCHM010.ZIP (7 KB) - PSpice Model

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Reference designs

TIDA-01051 — Reference Design Optimizing FPGA Utilization and Data Throughput for Automatic Test Equipment

The TIDA-01051 reference design is used to demonstrate optimized channel density, integration, power consumption, clock distribution and signal chain performance of very high channel count data acquisition (DAQ) systems such as those used in automatic test equipment (ATE). Using serializers, such (...)

Design guide: PDF

Schematic: PDF

Package Pins Download
PDIP (N) 14 View options
SOIC (D) 14 View options
SOP (NS) 14 View options
TSSOP (PW) 14 View options

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Information included:

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  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Information included:

  • Fab location
  • Assembly location

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