CD4081B Datenblatt, Produktinformationen und Support (2024)

Table of Contents
UND-Gatter, 4 Kanäle, 2 Eingänge, 3 bis 18 V CD4081B Produktdetails Ähnliche Produkte, die für Sie interessant sein könnten Technische Dokumentation Design und Entwicklung Bestellen & Qualität Support und Schulungen References
Startseite
  • parametric-filter Verstärker
  • parametric-filter Audio
  • parametric-filter Batteriemanagement-ICs
  • parametric-filter
  • parametric-filter DLP-Produkte
  • parametric-filter Datenwandler
  • parametric-filter
  • parametric-filter Schnittstelle
  • parametric-filter Isolierung
  • parametric-filter
  • parametric-filter
  • parametric-filter Motortreiber
  • parametric-filter Energiemanagement
  • parametric-filter
  • parametric-filter Sensoren
  • parametric-filter Schalter und Multiplexer
  • parametric-filter Drahtlose Konnektivität
Logikgatter
  • parametric-filter
  • parametric-filter
  • parametric-filter
  • parametric-filter Logikgatter
  • parametric-filter Speziallogik-ICs
  • parametric-filter
AND-Gatter
  • parametric-filter AND-Gatter
  • parametric-filter Kombinationsgatter
  • parametric-filter NAND-Gatter
  • parametric-filter NOR-Gatter
  • parametric-filter OR-Gatter
  • parametric-filter Spannungsumsetzungsgatter
  • parametric-filter XNOR-Gatter (Exklusives NOR)
  • parametric-filter XOR-Gatter (Exklusives OR)

Startseite

Logikgatter

AND-Gatter

AKTIV

UND-Gatter, 4 Kanäle, 2 Eingänge, 3 bis 18 V

Jetzt bestellen

Datenblatt

  • document-pdfAcrobat CD4073B, CD4081B, CD4082B TYPES datasheet (Rev. C) (Englisch)

CD4081B

AKTIV
Datenblatt Jetzt bestellen

Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 6.8 IOH (max) (mA) -6.8 Input type Standard CMOS Output type Push-Pull Features High speed (tpd 10- 50ns) Data rate (max) (Mbps) 8 Rating Catalog Operating temperature range (°C) -55 to 125

Technology family CD4000 Supply voltage (min) (V) 3 Supply voltage (max) (V) 18 Number of channels 4 Inputs per channel 2 IOL (max) (mA) 6.8 IOH (max) (mA) -6.8 Input type Standard CMOS Output type Push-Pull Features High speed (tpd 10- 50ns) Data rate (max) (Mbps) 8 Rating Catalog Operating temperature range (°C) -55 to 125

PDIP (N) 14 181.42 mm² 19.3 x 9.4 SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range: 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Standardized, symmetrical output characteristics
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

CD4073B Triple 3-Input AND Gate
CD4081B Quad 2-Input AND Gate
CD4082B Dual 4-Input AND Gate
Data sheet acquired from Harris Semiconductor
  • Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package-temperature range: 100 nA at 18 V and 25°C
  • Noise margin (full package-temperature range) =
    • 1 V at VDD = 5 V
    • 2 V at VDD = 10 V
    • 2.5 V at VDD = 15 V
  • Standardized, symmetrical output characteristics
  • 5-V, 10-V, and 15-V parametric ratings
  • Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

CD4073B Triple 3-Input AND Gate
CD4081B Quad 2-Input AND Gate
CD4082B Dual 4-Input AND Gate
Data sheet acquired from Harris Semiconductor

CD4073B, CD4081B and CD4082B AND gates, provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates.

The CD4073B, CD4081B, and CD4082B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4073B, CD4081B and CD4082B AND gates, provide the system designer with direct implementation of the AND function and supplement the existing family of CMOS gates.

The CD4073B, CD4081B, and CD4082B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

filter Andere AND-Gatter suchen

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open-in-new

Alternativen vergleichen

Drop-In-Ersatz mit verbesserter Funktionalität im Gegensatz zum verglichenen Baustein
SN74LVC08A AKTIV Vierkanal-UND-Gatter mit zwei Eingängen, 1,65 V bis 3,6 V Smaller voltage range (1.65V to 5.5V), shorter average propagation delay (5.5ns), higher average drive strength (24mA)

Technische Dokumentation

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Alle anzeigen 8
Typ Titel Datum
* Data sheet CD4073B, CD4081B, CD4082B TYPES datasheet (Rev. C) 21 Aug 2003
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 30 Apr 2024
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 03 Dez 2001

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Evaluierungsplatine

14-24-LOGIC-EVM — Generisches Logikprodukt-Evaluierungsmodul für 14-polige bis 24-polige D-, DB-, DGV-, DW-, DYY-, NS-

Das 14-24-LOGIC-EVM-Evaluierungsmodul (EVM) ist für die Unterstützung aller Logikgeräte konzipiert, die sich in einem 14-Pin- bis 24-Pin-D-, DW-, DB-, NS-, PW-, DYY- oder DGV-Gehäuse befinden.

Benutzerhandbuch: PDF | HTML

Nicht verfügbar auf TI.com

Simulationsmodell

CD4081B Behavioral SPICE Model (Rev. A)

SCHM010A.ZIP (7 KB) - PSpice Model

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Simulationsmodell

CD4081B PSPICE Model

SCHM010.ZIP (7 KB) - PSpice Model

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Referenzdesigns

TIDA-01051 — Referenzdesign zur Optimierung der FPGA-Auslastung und des Datendurchsatzes für automatische Prüfger

The TIDA-01051 reference design is used to demonstrate optimized channel density, integration, power consumption, clock distribution and signal chain performance of very high channel count data acquisition (DAQ) systems such as those used in automatic test equipment (ATE). Using serializers, such (...)

Design guide: PDF

Schaltplan: PDF

Gehäuse Pins Herunterladen
PDIP (N) 14 Optionen anzeigen
SOIC (D) 14 Optionen anzeigen
SOP (NS) 14 Optionen anzeigen
TSSOP (PW) 14 Optionen anzeigen

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